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| w WM8987l stereo codec for portable audio applications wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ production data, augut 2008, rev 4.0 copyright ? 2008 wolfson microelectronics plc description the WM8987l is a low power, high quality stereo codec designed for portable digital audio applications. the device integrates complete interfaces to stereo or mono microphones and a stereo btl (differential) or single-ended headset. external component requirements are reduced as no separate microphone or headphone amplifiers are required. advanced on-chip digital signal processing performs equalisation, 3-d sound enhancement and automatic level control for the microphone or line input. the WM8987l can operate as a master or a slave, with various master clock frequencies including 12 or 24mhz for usb devices, or standard 256f s rates like 12.288mhz and 24.576mhz. different audio sample rates such as 96khz, 48khz, 44.1khz are generated directly from the master clock without the need for an external pll. the WM8987l operates at supply voltages down to 1.8v, although the digital core can operate at voltages down to 1.42v to save power, and the maximum for all supplies is 3.6 volts. different sections of the chip can also be powered down under software control. the WM8987l is supplied in a very small and thin 4x4mm col package, ideal for use in ultra-portable and wearable systems. features ? dac snr 98db, adc 90db (?a? weighted) at 48khz, 3.3v ? on-chip headphone driver - single-ended or btl (differential) drive - >40mw output power on 16 ? / 3.3v - dac to 32 ? btl headphone: snr 86db, thd -66db ? complete stereo / mono microphone interface - differential or single-ended mic connection - programmable alc / noise gate ? digital equaliser ? low power - stereo playback 8 mw (1.8v / 1.5v supplies) - record and playback 13 mw (1.8v / 1.5v supplies) ? low supply voltages - analogue 1.8v to 3.6v - digital core: 1.42v to 3.6v - digital i/o: 1.8v to 3.6v ? 256fs / 384fs or usb master clock rates: 12mhz, 24mhz ? audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96khz generated internally from master clock ? 4x4mm col package ? register compatible with wm8750l applications ? wireless headsets ? portable music player / recorders block diagram
WM8987l production data w pd rev 4.0 august 2008 2 table of contents description .......................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 block diagram .................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................4 ordering information ..................................................................................4 pin description ................................................................................................5 absolute maximum ratings.........................................................................6 recommended operation conditions .....................................................6 electrical characteristics ......................................................................7 typical performance....................................................................................9 power consumption.............................................................................................. 9 headphone output thd versus power (typical)....................................... 10 output pga?s linearity ....................................................................................... 11 signal timing requirements .....................................................................12 system clock timing............................................................................................ 12 audio interface timing ? master mode ......................................................... 12 audio interface timing ? slave mode ............................................................ 13 control interface timing ? 3-wire mode ..................................................... 14 control interface timing ? 2-wire mode ..................................................... 15 internal power on reset circuit ..........................................................16 device description .......................................................................................17 introduction.......................................................................................................... 17 input signal path.................................................................................................. 17 automatic level control (alc) ....................................................................... 24 output signal path.............................................................................................. 28 analogue outputs ............................................................................................... 33 digital audio interface...................................................................................... 36 audio interface control .................................................................................. 39 clocking and sample rates .............................................................................. 41 control interface .............................................................................................. 43 power supplies ..................................................................................................... 44 power management ............................................................................................. 45 register map...................................................................................................47 digital filter characteristics ...............................................................48 terminology........................................................................................................... 48 dac filter responses ......................................................................................... 49 adc filter responses ......................................................................................... 50 de-emphasis filter responses ........................................................................ 51 highpass filter ..................................................................................................... 52 applications information .........................................................................53 recommended external components........................................................... 53 driving btl headsets........................................................................................... 54 driving single-ended headphones ................................................................. 54 microphone input configuration .................................................................. 56 line input configuration................................................................................... 57 minimising pop noise at the analogue outputs ........................................ 57 power management examples ......................................................................... 57 production data WM8987l w pd rev 4.0 august 2008 3 important notice ..........................................................................................59 address.................................................................................................................... 59 WM8987l production data w pd rev 4.0 august 2008 4 pin configuration ordering information order code temperature range package moisture sensitivity level peak soldering temperature WM8987lgeco/v -25c to +85c 28-lead col qfn (4x4mm) (pb-free) msl3 260c WM8987lgeco/rv -25c to +85c 28-lead col qfn (4x4mm) (pb-free, tape and reel) msl3 260c note: reel quantity = 3,500 production data WM8987l w pd rev 4.0 august 2008 5 pin description pin no name type description 1 mclk digital input master clock 2 dcvdd supply digital core supply 3 dbvdd supply digital buffer (i/o) supply 4 dgnd supply digital ground (return path for both dcvdd and dbvdd) 5 bclk digital input / output audio interface bit clock 6 dacdat digital input dac digital audio data 7 daclrc digital input / output audio interface left / right clock/clock out 8 adclrc digital input / output audio interface left / right clock 9 adcdat digital output adc digital audio data 10 out3 analogue output analogue output 3 (hpl- for btl headsets) 11 rout1 analogue output right output 1 (hpr+ for btl headsets) 12 hpgnd supply supply for analogue output drivers (rout1, l/rout2, out3) 13 rout2 analogue output right output 2 (hpr- for btl headsets) 14 lout2 analogue output left output 2 (hpl+ for btl headsets) 15 hpvdd supply supply for analogue output drivers (rout1, l/rout2, out3) 16 avdd supply analogue supply 17 agnd supply analogue ground (return path for avdd) 18 vref analogue output reference voltage decoupling capacitor 19 vmid analogue output midrail voltage decoupling capacitor 20 micbias analogue output microphone bias 21 rinput2 analogue input right channel input 2 22 linput2 analogue input left channel input 2 23 rinput1 analogue input right channel input 1 24 linput1 analogue input left channel input 1 25 mode digital input control interface selection 26 csb digital input chip select / device address selection 27 sdin digital input/output control interface data input / 2-wire acknowledge output 28 sclk digital input control interface clock input WM8987l production data w pd rev 4.0 august 2008 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max supply voltages -0.3v +3.63v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -25c +85c storage temperature after soldering -65c +150c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. dcvdd must be less than or equal to avdd and dbvdd. recommended operation conditions parameter symbol min typ max unit digital supply range (core) dcvdd 1.42 3.6 v digital supply range (buffer) dbvdd 1.7 3.6 v analogue supplies range avdd, hpvdd 1.8 3.6 v ground dgnd,agnd, hpgnd 0 v production data WM8987l w pd rev 4.0 august 2008 7 electrical characteristics test conditions dcvdd = 1.5v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, adcosr = dacosr = 1 (64 fs), 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit analogue inputs (linput1, rinput1, linput2, rinput2) to adc out avdd = 3.3v 1.0 full scale input signal level (for adc 0db input at 0db gain) v infs avdd = 1.8v 0.545 v rms l/rinput1 to adc, pga gain = 0db 22 l/rinput1 to adc, pga gain = +30db 1.5 l/rinput1 unused dc measurement 16 input resistance l/rinput1 unused 17 k ? input capacitance 10 pf avdd = 3.3v 80 90 signal to noise ratio (a-weighted) snr avdd = 1.8v 87 db -1dbfs input, avdd = 3.3v -80 0.01 total harmonic distortion thd -1dbfs input, avdd = 1.8v -70 0.03 db % adc channel separation 1khz signal 88 db channel matching 1khz signal 0.04 % dac to btl headset drive (left=lout2/out3, right=rout1/rout2) full scale output voltage across btl load 0dbfs lout2-out3, rout1-rout2 avdd/1.65 vrms output power per channel p o output power is very closely correlated with thd; see below. avdd=hpvdd=1.8v, r l =32 ? , p o =5mw -66 0.05 -58 0.13 total harmonic distortion thd avdd=hpvdd =1.8v, r l =16 ? , p o =5mw -62 0.08 db % signal to noise ratio (a-weighted) snr avdd=hpvdd =1.8v, r l =32 ? 80 86 db dac to single-ended headset drive (lout2/rout2, using capacitors) full scale output voltage 0dbfs lout2, rout2 avdd/3.3 vrms output power per channel p o output power is very closely correlated with thd; see below. hpvdd=3.3v, r l =32 ? , p o =5mw -61 0.09 -52 0.25 total harmonic distortion thd hpvdd=3.3v, r l =16 ? , p o =5mw -60 0.1 -52 0.25 db % signal to noise ratio (a-weighted) snr avdd=hpvdd =3.3v 92 98 db dac to single-ended headset drive ( capless, using out3 as headphone ground) full scale output voltage 0dbfs lout2-out3, rout2-out3 avdd/3.3 vrms output power per channel p o output power is very closely correlated with thd; see below. hpvdd=3.3v, r l =32 ? , p o =5mw -61 0.09 total harmonic distortion thd hpvdd=3.3v, r l =16 ? , p o =5mw -60 0.1 db % WM8987l production data w pd rev 4.0 august 2008 8 test conditions dcvdd = 1.5v, dbvdd = 3.3v, avdd = hpvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, pga gain = 0db, adcosr = dacosr = 1 (64 fs), 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit signal to noise ratio (a-weighted) snr avdd=hpvdd =3.3v 98 db analogue reference levels midrail reference voltage vmid ?3% avdd/2 +3% v buffered reference voltage vref ?3% avdd/2 +3% v microphone bias bias voltage v micbias 3ma load current ?5% 0.9 avdd + 5% v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ hz digital input / output input high level v ih 0.7 dbvdd v input low level v il 0.3 dbvdd v output high level v oh i oh = +1ma 0.9 dbvdd v output low level v ol i ol = -1ma 0.1 dbvdd v production data WM8987l w pd rev 4.0 august 2008 9 typical performance power consumption the power consumption of the WM8987l depends on the following factors. ? supply voltages: reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of the WM8987l. ? operating mode: significant power savings can be achieved by always disabling parts of the WM8987l that are not used (e.g. mic pre-amps, unused outputs, dac, adc, etc.) control register r23 other settings tot. power code bit vmidsel vref ainl ainr adcl adcr micb digenb dacl dacr rout1 lout2 rout2 mono out3 out3sw rout2in v adcosr dacosr vsel vi (ma)vi (ma)vi (ma)vi (ma) mw pof-01 off 0000000010000000000011 clo cks stopped 3.3 0.000 3.3 0.010 3.3 0.000 3.3 0.000 0.033 pof-02 01 2.7 0.000 2.0 0.007 2.5 0.000 2.7 0.000 0.014 pof-03 00 1.8 0.000 1.5 0.007 1.8 0.000 1.8 0.000 0.011 pst-01 standby 1010000010000000000011 interface stopped 3.3 0.482 3.3 0.011 3.3 0.000 3.3 0.000 1.627 pst-02 (500 kohm vmid string) 01 2.7 0.310 2.0 0.008 2.5 0.000 2.7 0.000 0.853 pst-03 00 1.8 0.184 1.5 0.007 1.8 0.000 1.8 0.000 0.342 ppb-01 btl headset stereo playback 01 10000001111111111111 3.3 2.573 3.3 4.601 3.3 0.248 3.3 4.291 38.653 ppb-02 0.1mw/channel into 32 ohm load 01 2.7 2.052 2.0 2.371 2.5 0.175 2.7 4.314 22.368 ppb-03 00 1.8 1.297 1.5 1.750 1.8 0.119 1.8 3.879 12.156 pps-01 single-ended headset stereo playback 01 10000001101100001111 3.3 2.232 3.3 4.662 3.3 0.248 3.3 2.005 30.185 pps-02 0.1mw/channel into 32 ohm load 01 2.7 1.778 2.0 2.411 2.5 0.175 2.7 2.021 15.517 pps-03 00 1.8 1.126 1.5 1.758 1.8 0.119 1.8 1.856 8.219 ppc-01 single-ended headset stereo playback 0110000001101101001111 3.3 2.229 3.3 4.662 3.3 0.248 3.3 4.007 36.782 ppc-02 (capless mode using out3) 01 2.7 1.776 2.0 2.408 2.5 0.175 2.7 4.007 20.868 ppc-03 0.1mw/channel into 32 ohm load 00 1.8 1.126 1.5 1.757 1.8 0.119 1.8 3.674 11.490 prd-01 differential mono mic record 0111010100000000001111 linsel=11 3.3 3.551 3.3 4.883 3.3 0.298 3.3 0.000 28.816 prd-02 (linput1-rinput1) 01 lmicboost=10 2.7 3.077 2.0 2.255 2.5 0.213 2.7 0.000 13.350 prd-03 00 datsel=01 1.8 2.388 1.5 1.584 1.8 0.148 1.8 0.000 6.941 prs-01 single-ended mono mic record 0111010100000000001111 lmicboost=10 3.3 3.196 3.3 4.888 3.3 0.295 3.3 0.000 27.651 prs-02 (from linput1) 01 datsel=01 2.7 2.799 2.0 2.270 2.5 0.212 2.7 0.000 12.627 prs-03 00 1.8 2.221 1.5 1.588 1.8 0.146 1.8 0.000 6.643 prl-01 single-ended stereo line record 0111111000000000001111 3.3 4.532 3.3 4.917 3.3 0.287 3.3 0.000 32.129 prl-02 (from l/rinput1) 01 2.7 4.037 2.0 2.281 2.5 0.206 2.7 0.000 15.977 prl-03 00 1.8 3.313 1.5 1.605 1.8 0.142 1.8 0.000 8.627 pdl-01 simultaneous record and playback 0111111001101100001111 3.3 6.295 3.3 7.836 3.3 0.286 3.3 0.679 49.817 pdl-02 (stereo, line-in / line-out) 01 2.7 5.454 2.0 3.837 2.5 0.206 2.7 0.711 24.835 pdl-03 00 1.8 4.212 1.5 2.760 1.8 0.142 1.8 0.364 12.632 r25 (19h) dcvdd dbvdd hpvdd r26 (1ah) avdd r24 (18h) table 1 typical supply current consumption notes: 1. all figures are at t a = +25 o c, slave mode, fs = 48khz, mclk = 12.288 mhz (256fs), with zero signal (quiescent) 2. the power dissipated in the headphone or speaker is not included in the above table. WM8987l production data w pd rev 4.0 august 2008 10 headphone output thd versus power (typical) WM8987 thd+n v output power btl headset drive 0.01 0.1 1 10 100 0.1 1 10 100 output power (mw) thd+n (%) 16ohm 3.3v 16ohm 2.7v 16ohm 1.8v 32ohm 3.3v 32ohm 2.7v 32ohm 1.8v WM8987 thd+n v output power single ended headset drive (ac coupled) 0.01 0.1 1 10 0.1 1 10 100 output power (mw) thd+n (%) 16ohm 3.3v 16ohm 2.7v 16ohm 1.8v 32ohm 3.3v 32ohm 2.7v 32ohm 1.8v WM8987 thd+n v output power single ended headset drive (capless) 0.01 0.1 1 10 0.1 1 10 100 output power (mw) thd+n (%) 16ohm 3.3v 16ohm 2.7v 16ohm 1.8v 32ohm 3.3v 32ohm 2.7v 32ohm 1.8v production data WM8987l w pd rev 4.0 august 2008 11 output pga?s linearity output pga gains -70.000 -60.000 -50.000 -40.000 -30.000 -20.000 -10.000 0.000 10.000 40 50 60 70 80 90 100 110 120 130 xxxvol register setting (binary) measured gain [db] rout1 lout2 rout2 monoout output pga gain step size 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 40 50 60 70 80 90 100 110 120 130 xxxvol register setting (binary) step size [db] rout1 lout2 rout2 monoout WM8987l production data w pd rev 4.0 august 2008 12 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 1 system clock timing requirements test conditions clkdiv2=0 , dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 384fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 21 ns mclk system clock pulse width low t mclkh 21 ns mclk system clock cycle time t mclky 54 ns mclk duty cycle t mclkds 60:40 40:60 test conditions clkdiv2=1 , dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode fs = 48khz, mclk = 384fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit system clock timing information mclk system clock pulse width high t mclkl 10 ns mclk system clock pulse width low t mclkh 10 ns mclk system clock cycle time t mclky 27 ns audio interface timing ? master mode bclk (output) adcdat adclrc/ daclrc (outputs) t dl dacdat t dda t dht t dst figure 2 digital audio data timing ? master mode (see control interface) production data WM8987l w pd rev 4.0 august 2008 13 test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, master mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit bit clock timing information bclk rise time (10pf load) t bclkr 3 ns bclk fall time (10pf load) t bclkf 3 ns bclk duty cycle (normal mode, bclk = mclk/n) t bclkds 50:50 bclk duty cycle (usb mode, bclk = mclk) t bclkds t mclkds audio data input timing information adclrc/daclrc propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 40 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns audio interface timing ? slave mode bclk daclrc/ adclrc t bch t bcl t bcy dacdat adcdat t lrsu t ds t lrh t dh t dd figure 3 digital audio data timing ? slave mode test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns adclrc/daclrc set-up time to bclk rising edge t lrsu 10 ns adclrc/daclrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 10 ns note: bclk period should always be greater than or equal to mclk period. WM8987l production data w pd rev 4.0 august 2008 14 control interface timing ? 3-wire mode csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 4 control interface timing ? 3-wire serial control mode test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns production data WM8987l w pd rev 4.0 august 2008 15 control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 5 control interface timing ? 2-wire serial control mode test conditions dcvdd = 1.42v, dbvdd = 3.3v, dgnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns WM8987l production data w pd rev 4.0 august 2008 16 internal power on reset circuit vdd t1 gnd avdd dcvdd dgnd internal porb power on reset circuit figure 6 internal power on reset circuit schematic the WM8987l includes an internal power-on-reset circuit, as shown below, which is used to reset the digital logic into a default state after power up. the power on reset circuit is powered from dcvdd and monitors dcvdd and avdd. it asserts porb low if dcvdd or avdd are below a minimum threshold. figure 7 typical power-up sequence figure 7 shows a typical power-up sequence. when dcvdd and avdd rise above the minimum thresholds, vpord_dcvdd and vpord_avdd, there is enough voltage for the circuit to guarantee the power on reset is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when dcvdd rises to vpor_dcvdd_on and avdd rises to vpor_avdd_on, porb is released high and all registers are in their default state and writes to the control interface may take place. if dcvdd and avdd rise at different rates then porb will only be released when dcvdd and avdd have both exceeded the vpor_dcvdd_on and vpor_avdd_on thresholds. on power down, porb is asserted low whenever dcvdd drops below the minimum threshold vpor_dcvdd_off or avdd drops below the minimum threshold vpor_avdd_off. symbol min typ max unit v pord_dcvdd 0.4 0.6 0.8 v v por_dcvdd_on 0.9 1.26 1.6 v v por_avdd_on 0.5 0.7 0.9 v v por_avdd_off 0.4 0.6 0.8 v table 2 typical por operation (typical values, not tested) production data WM8987l w pd rev 4.0 august 2008 17 device description introduction the WM8987l is a low power audio codec offering a combination of high quality audio, advanced features, low power and small size. these characteristics make it ideal for portable digital audio applications such as mp3 and minidisk player / recorders. stereo 24-bit multi-bit delta sigma adcs and dacs are used with oversampling digital interpolation and decimation filters. the device includes three stereo analogue inputs that can be switched internally. each can be used as either a line level input or microphone input and linput1/rinput1 and linput2/rinput2 can be configured as mono differential inputs. a programmable gain amplifier with automatic level control (alc) keeps the recording volume constant. the on-chip stereo adc and dac are of a high quality using a multi-bit, low-order oversampling architecture to deliver optimum performance with low power consumption. the dac output signal first enters an analogue mixer where an analogue input and/or the post-alc signal can be added to it. this mix is available on line and headphone outputs. the WM8987l has a configurable digital audio interface where adc data can be read and digital audio playback data fed to the dac. it supports a number of audio data formats including i 2 s, dsp mode (a burst mode in which frame sync plus 2 data packed words are transmitted), and msb-first, left justified. it can operate in master or slave modes. the WM8987l uses a unique clocking scheme that can generate many commonly used audio sample rates from either a 12.00mhz usb clock or an industry standard 256/384 f s clock. this feature eliminates the common requirement for an external phase-locked loop (pll) in applications where the master clock is not an integer multiple of the sample rate. sample rates of 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz, 88.2khz and 96khz can be generated. the digital filters used for recording and playback are optimised for each sampling rate used. to allow full software control over all its features, the WM8987l offers a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. the design of the WM8987l has given much attention to power consumption without compromising performance. it operates at very low voltages, and includes the ability to power off parts of the circuitry under software control, including standby and power off modes. input signal path the input signal path for each channel consists of a switch to select between three analogue inputs, followed by a pga (programmable gain amplifier) and an optional microphone gain boost. a differential input of either (linput1 ? rinput1) or (linput2 ? rinput2) may also be selected. the gain of the pga can be controlled either by the user or by the on-chip alc function (see automatic level control). the signal then enters an adc where it is digitised. alternatively, the two channels can also be mixed in the analogue domain and digitised in one adc while the other adc is switched off. the mono-mix signal appears on both digital output channels. signal inputs the WM8987l has two sets of high impedance, low capacitance ac coupled analogue inputs, linput1/rinput1 and linput2/rinput2. inputs can be configured as microphone or line level by enabling or disabling the microphone gain boost. linsel and rinsel control bits (see table 4) are used to select independently between external inputs and internally generated difference signals (linput1-rinput1 or linput2-rinput2). the choice of difference signal, linput1-rinput1 or linput2-rinput2 is made using the ds bit (see below). register address bit label default description r31 (1fh) adc input mode 8 ds 0 differential input select 0: linput1 - rinput1 1: linput2 ? rinput2 table 3 differential input select WM8987l production data w pd rev 4.0 august 2008 18 as an example, the WM8987l can be set up to convert one differential and one single ended mono signal by applying the differential signal to linput1/rinput1 and the single ended signal to rinput2. by setting linsel to l-r differential (see table 4), ds to linput1 - rinput1 and rinsel to rinput2, each mono signal can then be routed to a separate adc or bypass pat the signal inputs are biased internally to the reference voltage vref. whenever the line inputs are muted or the device placed into standby mode, the inputs are kept biased to vref using special anti-thump circuitry. this reduces any audible clicks that may otherwise be heard when changing inputs. dc measurement for dc measurements (for example, battery voltage monitoring), the input signal at the linput1 and/or rinput1 pins can be taken directly into the respective adc, bypassing both pga and microphone boost. the adc output then becomes unsigned relative to avdd, instead of being a signed (two?s complement) number relative to vref. setting l/rdcm will override l/rinsel. the input range for dc measurement is agnd to avdd. register address bit label default description 7:6 linsel 00 left channel input select 00 = linput1 01 = linput2 10 = reserved 11 = l-r differential (either linput1- rinput1 or linput2-rinput2, selected by ds) r32 (20h) adc signal path control (left) 5:4 lmicboost 00 left channel microphone gain boost 00 = boost off (bypassed) 01 = 13db boost 10 = 20db boost 11 = 29db boost 7:6 rinsel 00 right channel input select 00 = rinput1 01 = rinput2 10 = reserved 11 = l-r differential (either linput1- rinput1 or linput2-rinput2, selected by ds) r33 (21h) adc signal path control (right) 5:4 rmicboost 00 right channel microphone gain boost 00 = boost off (bypassed) 01 = 13db boost 10 = 20db boost 11 = 29db boost table 4 input software control register address bit label default description 5 rdcm 0 right channel dc measurement 0 = normal operation, pga enabled 1 = measure dc level on rinput1 r31 (1fh) adc input mode 4 ldcm 0 left channel dc measurement 0 = normal operation, pga enabled 1 = measure dc level on linput1 table 5 dc measurement select production data WM8987l w pd rev 4.0 august 2008 19 mono mixing the stereo adc can operate as a stereo or mono device, or the two channels can be mixed to mono, either in the analogue domain (i.e. before the adc) or in the digital domain (after the adc). monomix selects the mode of operation. for analogue mono mix either the left or right channel adc can be used, allowing the unused adc to be powered off or used for a dc measurement conversion. the user also has the flexibility to select the data output from the audio interface using datsel. the default is for left and right channel adc data to be output, but the interface may also be configured so that e.g. left channel adc data is output as both left and right data for when an analogue mono mix is selected. note: if dc measurement is selected this overrides the monomix selection. register address bit label default description r31 (1fh) adc input mode 7:6 monomix [1:0] 00 00: stereo 01: analogue mono mix (using left adc) 10: analogue mono mix (using right adc) 11: digital mono mix table 6 mono mixing register address bit label default description r23 (17h) additional control (1) 3:2 datsel [1:0] 00 00: left data=left adc; right data =right adc 01: left data =left adc; right data = left adc 10: left data = right adc; right data =right adc 11: left data = right adc; right data = left adc table 7 adc data output configuration the micbias output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external components. the output can be enabled or disabled using the micb control bit (see also the ?power management? section). register address bit label default description r25 (19h) power management (1) 1 micb 0 microphone bias enable 0 = off (high impedance output) 1 = on table 8 microphone bias control the internal micbias circuitry is shown below. note that this is a maximum source current capability for micbias is 3ma. the external biasing resistors therefore must be large enough to limit the micbias current to 3ma. agnd micbias = 1.8 x vmid = 0.9 x avdd vmid internal resistor internal resistor micb figure 8 microphone bias schematic WM8987l production data w pd rev 4.0 august 2008 20 pga control the pga matches the input signal level to the adc input range. the pga gain is logarithmically adjustable from +30db to ?17.25db in 0.75db steps. each pga can be controlled either by the user or by the alc function (see ?automatic level control?). when alc is enabled for one or both channels, then writing to the corresponding pga control register has no effect. the gain is independently adjustable on both right and left line inputs. additionally, by controlling the register bits livu and rivu, the left and right gain settings can be simultaneously updated. setting the lzcen and rzcen bits enables a zero-cross detector which ensures that pga gain changes only occur when the signal is at zero, eliminating any zipper noise. if zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. this function may be enabled by setting toen in register r23 (17h). the inputs can also be muted in the analogue domain under software control. the software control registers are shown in table 9. if zero crossing is enabled, it is necessary to enable zero cross timeout to un-mute the input pgas. this is because their outputs will not cross zero when muted. alternatively, zero cross can be disabled before sending the un-mute command. register address bit label default description 8 livu 0 left volume update 0 = store linvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = linvol, right = intermediate latch) 7 linmute 1 left channel input analogue mute 1 = enable mute 0 = disable mute note: livu must be set to un-mute. 6 lzcen 0 left channel zero cross detector 1 = change gain on zero cross only 0 = change gain immediately r0 (00h) left channel pga 5:0 linvol [5:0] 010111 ( 0db ) left channel input volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db 8 rivu 0 right volume update 0 = store rinvol in intermediate latch (no gain change) 1 = update left and right channel gains (right = rinvol, left = intermediate latch) 7 rinmute 1 right channel input analogue mute 1 = enable mute 0 = disable mute note: rivu must be set to un-mute. 6 rzcen 0 right channel zero cross detector 1 = change gain on zero cross only 0 = change gain immediately r1 (01h) right channel pga 5:0 rinvol [5:0] 010111 ( 0db ) right channel input volume control 111111 = +30db 111110 = +29.25db . . 0.75db steps down to 000000 = -17.25db r23 (17h) additional control (1) 0 toen 0 timeout enable 0 : timeout disabled 1 : timeout enabled table 9 input pga software control production data WM8987l w pd rev 4.0 august 2008 21 analogue to digital converter (adc) the WM8987l uses a multi-bit, oversampled sigma-delta adc for each channel. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. with a 3.3v supply voltage, the full scale level is 1.0 volts r.m.s. any voltage greater than full scale may overload the adc and cause distortion. adc digital filter the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. the digital filter path is illustrated in figure 9. from adc digital hpf digital filter to digital a udio interface digital decimator a dchpd figure 9 adc digital filter the adc digital filters contain a digital high pass filter, selectable via software control. the high-pass filter response is detailed in the digital filter characteristics section. when the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. by setting hpor, the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. if the dc offset is changed, the stored and subtracted value will not change unless the high-pass filter is enabled. this feature can be used for calibration purposes. in addition the high pass filter may be enabled separately on the left and right channels (see table 11). the output data format can be programmed by the user to accommodate stereo or monophonic recording on both inputs. the polarity of the output signal can also be changed under software control. the software control is shown in table 10. WM8987l production data w pd rev 4.0 august 2008 22 register address bit label default description 6:5 adcpol [1:0] 00 00 = polarity not inverted 01 = l polarity invert 10 = r polarity invert 11 = l and r polarity invert 4 hpor 0 store dc offset when high-pass filter disabled 1 = store offset 0 = clear offset adc high-pass filter enable (digital) hpflren = 0 1 = disable high-pass filter on left and right channels 0 = enable high-pass filter on left and right channels r5 (05h) adc and dac control 0 adchpd 0 hpflren = 1 0 = high-pass enabled on left, disabled on right 1 = high-pass enabled on right, disabled on left r27 (1bh) 5 hpflren 0 adc high-pass filter left or right enable 0 = high-pass filter enable/disable on left and right channels controlled by adchpd 1 = high-pass filter enabled on left or right channel, as selected by adchpd table 10 adc signal path control hpflren adchpd high pass mode 0 0 high-pass filter enabled on left and right channels 0 1 high-pass filter disabled on left and right channels 1 0 high-pass filter enabled on left channel, disabled on right channel 1 1 high-pass filter disabled on left channel, enabled on right channel table 11 adc high pass filter enable modes production data WM8987l w pd rev 4.0 august 2008 23 digital adc volume control the output of the adcs can be digitally amplified or attenuated over a range from ?97db to +30db in 0.5db steps. the volume of each channel can be controlled separately. the gain for a given eight-bit code x is given by: 0.5 (x-195) db for 1 x 255; mute for x = 0 the lavu and ravu control bits control the loading of digital volume control data. when lavu or ravu are set to 0, the ladcvol or radcvol control data will be loaded into the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when either lavu or ravu are set to 1. this makes it possible to update the gain of both channels simultaneously. register address bit label default description 7:0 ladcvol [7:0] 11000011 ( 0db ) left adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db r21 (15h) left adc digital volume 8 lavu 0 left adc volume update 0 = store ladcvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ladcvol, right = intermediate latch) 7:0 radcvol [7:0] 11000011 ( 0db ) right adc digital volume control 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ... 0.5db steps up to 1111 1111 = +30db r22 (16h) right adc digital volume 8 ravu 0 right adc volume update 0 = store radcvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = radcvol) table 12 adc digital volume control WM8987l production data w pd rev 4.0 august 2008 24 automatic level control (alc) the WM8987l has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. note that when the alc function is enabled, the settings of registers 0 and 1 (linvol, livu, lizc, linmute, rinvol, rivu, rizc and rinmute) are ignored. hold time decay time attack time input signal signal after alc pga gain alc target level figure 10 alc operation the alc function is enabled using the alcsel control bits. when enabled, the recording volume can be programmed between ?6db and ?28.5db (relative to adc full scale) using the alcl register bits. an upper limit for the pga gain can be imposed by setting the maxgain control bits. hld, dcy and atk control the hold, decay and attack times, respectively: hold time is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. alternatively, the hold time can also be set to zero. the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. decay (gain ramp-up) time is the time that it takes for the pga gain to ramp up across 90% of its range (e.g. from ?15b up to 27.75db). the time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the decay time. the decay time can be programmed in power-of-two (2 n ) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. attack (gain ramp-down) time is the time that it takes for the pga gain to ramp down across 90% of its range (e.g. from 27.75db down to -15b gain). the time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. if the gain adjustment is small, it will be shorter than the attack time. the attack time can be programmed in power-of-two (2 n ) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. when operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right pgas, so that the stereo image is preserved. however, the alc function can also be enabled on one channel only. in this case, only one pga is controlled by the alc mechanism, while the other channel runs independently with its pga gain set through the control register. when one adc channel is unused or used for dc measurement, the peak detector disregards that channel. the alc function can also operate when the two adc outputs are mixed to mono in the digital domain, but not if they are mixed to mono in the analogue domain, before entering the adcs. production data WM8987l w pd rev 4.0 august 2008 25 register address bit label default description 8:7 alcsel [1:0] 00 (off) alc function select 00 = alc off (pga gain set by register) 01 = right channel only 10 = left channel only 11 = stereo (pga registers unused) note: ensure that linvol and rinvol settings (reg. 0 and 1) are the same before entering this mode. 6:4 maxgain [2:0] 111 (+30db) set maximum gain of pga 111 : +30db 110 : +24db ?.(-6db steps) 001 : -6db 000 : -12db r17 (11h) alc control 1 3:0 alcl [3:0] 1011 (-12db) alc target ? sets signal level at adc input 0000 = -28.5db fs 0001 = -27.0db fs ? (1.5db steps) 1110 = -7.5db fs 1111 = -6db fs 7 alczc 0 (zero cross off) alc uses zero cross detection circuit. r18 (12h) alc control 2 3:0 hld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s 7:4 dcy [3:0] 0011 (192ms) alc decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ? (time doubles with every step) 1010 or higher = 24.58s r19 (13h) alc control 3 3:0 atk [3:0] 0010 (24ms) alc attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ? (time doubles with every step) 1010 or higher = 6.14s table 13 alc control note: the alc function should not be used when the combined signal gain (mic boost and pga) is greater than 30db. for correct alc operation, it is recommended to use single-ended input signals as opposed to using the differential input circuit. WM8987l production data w pd rev 4.0 august 2008 26 peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), the pga gain is ramped down at the maximum attack rate (as when atk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. note: if atk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used. noise gate when the signal is very quiet and consists mainly of noise, the alc function may cause ?noise pumping?, i.e. loud hissing noise during silence periods. the WM8987l has a noise gate function that prevents noise pumping by comparing the signal level at the l/rinput1 and/or l/rinput2 pins against a noise gate threshold, ngth. the noise gate cuts in when: ? signal level at adc [db] < ngth [db] + pga gain [db] + mic boost gain [db] this is equivalent to: ? signal level at input pin [db] < ngth [db] the adc output can then either be muted or alternatively, the pga gain can be held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 1.5db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set?up of the function. note that the noise gate only works in conjunction with the alc function, and always operates on the same channel(s) as the alc (left, right, both, or none). register address bit label default description 7:3 ngth [4:0] 00000 noise gate threshold 00000 -76.5dbfs 00001 -75dbfs ? 1.5 db steps 11110 -31.5dbfs 11111 -30dbfs 2:1 ngg [1:0] 00 noise gate type x0 = pga gain held constant 01 = mute adc output 11 = reserved (do not use this setting) r20 (14h) noise gate control 0 ngat 0 noise gate function enable 1 = enable 0 = disable table 14 noise gate control note: the performance of the adc may degrade at high input signal levels if the monitor bypass mux is selected with mic boost and alc enabled. production data WM8987l w pd rev 4.0 august 2008 27 3d stereo enhancement the WM8987l has a digital 3d enhancement option to artificially increase the separation between the left and right channels. this effect can be used for recording or playback, but not for both simultaneously. selection of 3d for record or playback is controlled by register bit mode3d. important: switching the 3d filter from record to playback or from playback to record may only be done when adc and dac are disabled. the WM8987l control interface will only allow mode3d to be changed when adc and dac are disabled (i.e. bits adcl, adcr, dacl and dacr in reg. 26 / 1ah are all zero). the 3d enhancement function is activated by the 3den bit, and has two programmable parameters. the 3ddepth setting controls the degree of stereo expansion. additionally, one of four filter characteristics can be selected for the 3d processing, using the 3dvc and 3dlc control bits. register address bit label default description 7 mode3d 0 playback/record 3d select 0 = 3d selected for record 1 = 3d selected for playback 6 3duc 0 upper cut-off frequency 0 = high (2.2khz at 48khz sampling) 1 = low (1.5khz at 48khz sampling) 5 3dlc 0 lower cut-off frequency 0 = low (200hz at 48khz sampling) 1 = high (500hz at 48khz sampling) 4:1 3ddepth [3:0] 0000 stereo depth 0000: 0% (minimum 3d effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3d effect) r16 (10h) 3d enhance 0 3den 0 3d function enable 1: enabled 0: disabled table 15 3d stereo enhancement function when 3d enhancement is enabled (and/or the graphic equaliser for playback) it may be necessary to attenuate the signal by 6db to avoid limiting. this is a user selectable function, enabled by setting adcdiv2 for the record path and dacdiv2 for the playback path. register address bit label default description 8 adcdiv2 0 adc 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled r5 (05h) adc and dac control 7 dacdiv2 0 dac 6db attenuate enable 0 = disabled (0db) 1 = -6db enabled table 16 adc and dac 6db attenuation select WM8987l production data w pd rev 4.0 august 2008 28 output signal path the WM8987l output signal paths consist of digital filters, dacs, analogue mixers and output drivers. the digital filters and dacs are enabled when the WM8987l is in ?playback only? or ?record and playback? mode. the mixers and output drivers can be separately enabled by individual control bits (see analogue outputs). thus it is possible to utilise the analogue mixing and amplification provided by the WM8987l, irrespective of whether the dacs are running or not. the WM8987l receives digital input data on the dacdat pin. the digital filter block processes the data to provide the following functions: ? digital volume control ? graphic equaliser and dynamic bass boost ? sigma-delta modulation two high performance sigma-delta audio dacs convert the digital data into two analogue signals (left and right). these can then be mixed with analogue signals from the l/rinput1 and l/rinput2 pins, and the mix is fed to the output drivers, rout1, lout2/rout2 and out3. digital dac volume control the signal volume from each dac can be controlled digitally, in the same way as the adc volume (see digital adc volume control). the gain and attenuation range is ?127db to 0db in 0.5db steps. the level of attenuation for an eight-bit code x is given by: 0.5 (x-255) db for 1 x 255; mute for x = 0 the ldvu and rdvu control bits control the loading of digital volume control data. when ldvu or rdvu are set to 0, the ldacvol or rdacvol control data is loaded into an intermediate register, but the actual gain does not change. both left and right gain settings are updated simultaneously when either ldvu or rdvu are set to 1. register address bit label default description 8 ldvu 0 left dac volume update 0 = store ldacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = ldacvol, right = intermediate latch) r10 (0ah) left channel digital volume 7:0 ldacvol [7:0] 11111111 ( 0db ) left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db 8 rdvu 0 right dac volume update 0 = store rdacvol in intermediate latch (no gain change) 1 = update left and right channel gains (left = intermediate latch, right = rdacvol) r11 (0bh) right channel digital volume 7:0 rdacvol [7:0] 11111111 ( 0db ) right dac digital volume control similar to ldacvol table 17 digital volume control production data WM8987l w pd rev 4.0 august 2008 29 graphic equaliser the WM8987l has a digital graphic equaliser and adaptive bass boost function. this function operates on digital audio data before it is passed to the audio dacs. bass enhancement can take two different forms: ? linear bass control: bass signals are amplified or attenuated by a user programmable gain. this is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. ? adaptive bass boost: the bass volume is amplified by a variable gain. when the bass volume is low, it is boosted more than when the bass volume is high. this method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. treble control applies a user programmable gain, without any adaptive boost function. bass and treble control are completely independent with separately programmable gains and filter characteristics. register address bit label default description 7 bb 0 bass boost 0 = linear bass control 1 = adaptive bass boost 6 bc 0 bass filter characteristic 0 = low cutoff (130hz at 48khz sampling) 1 = high cutoff (200hz at 48khz sampling) bass intensity code bb=0 bb=1 0000 +9db 15 (max) 0001 +9db 14 0010 +7.5db 13 0011 +6db 12 0100 +4.5db 11 0101 +3db 10 0110 +1.5db 9 0111 0db 8 1000 -1.5db 7 1001 -3db 6 1010 -4.5db 5 1011 -6db 4 1100 -6db 3 1101 -6db 2 1110 -6db 1 r12 (0ch) bass control 3:0 bass [3:0] 1111 (disabled) 1111 bypass (off) 6 tc 0 treble filter characteristic 0 = high cutoff (8khz at 48khz sampling) 1 = low cutoff (4khz at 48khz sampling) r13 (0dh) treble control 3:0 trbl [3:0] 1111 (disabled) treble intensity 0000 or 0001 = +9db 0010 = +7.5db ? (1.5db steps) 1011 to 1110 = -6db 1111 = disable table 18 graphic equaliser WM8987l production data w pd rev 4.0 august 2008 30 digital to analogue converter (dac) after passing through the graphic equaliser filters, digital ?de-emphasis? can be applied to the audio data if necessary (e.g. when the data comes from a cd with pre-emphasis used in the recording). de-emphasis filtering is available for sample rates of 48khz, 44.1khz and 32khz. the WM8987l also has a soft mute function, which gradually attenuates the volume of the digital signal to zero. when removed, the gain will return to the original setting. this function is enabled by default. to play back an audio signal, it must first be disabled by setting the dacmu bit to zero. register address bit label default description 2:1 deemp [1:0] 00 de-emphasis control 11 = 48khz sample rate 10 = 44.1khz sample rate 01 = 32khz sample rate 00 = no de-emphasis r5 (05h) adc and dac control 3 dacmu 1 digital soft mute 1 = mute 0 = no mute (signal active) table 19 dac control the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dynamic element matching technique for high linearity and low distortion. in normal operation, the left and right channel digital audio data is converted to analogue in two separate dacs. however, it is also possible to disable one channel, so that the same signal (left or right) appears on both analogue output channels. additionally, there is a mono-mix mode where the two audio channels are mixed together digitally and then converted to analogue using only one dac, while the other dac is switched off. the mono-mix signal can be selected to appear on both analogue output channels. the dac output defaults to non-inverted. setting dacinv will invert the dac output phase on both left and right channels. register address bit label default description 5:4 dmonomix [1:0] 00 dac mono mix 00: stereo 01: mono ((l+r)/2) into dacl, ?0? into dacr 10: mono ((l+r)/2) into dacr, ?0? into dacl 11: mono ((l+r)/2) into dacl and dacr r23 (17h) additional control (1) 1 dacinv 0 dac phase invert 0 : non-inverted 1 : inverted table 20 dac mono mix and phase invert select production data WM8987l w pd rev 4.0 august 2008 31 output mixers the WM8987l provides the option to mix the dac output signal with analogue line-in signals from the l/rinput1/2, rinput1/2 pins or a mono differential input (linput1 ? rinput1 or linput2 ? rinput2), selected by ds (see table 3). the level of the mixed-in signals can be controlled with pgas (programmable gain amplifiers). the mono mixer is designed to allow a number of signal combinations to be mixed, including the possibility of mixing both the right and left channels together to produce a mono output. to prevent overloading of the mixer when full-scale dac left and right signals are input, the mixer inputs from the dac outputs each have a fixed gain of -6db. the bypass path inputs to the mono mixer have variable gain as determined by r38/r39 bits [6:4]. register address bit label default description r34 (22h) left mixer (1) 2:0 lmixsel 000 left input selection for output mix 000 = linput1 001 = linput2 011 = left adc input (after pga / micboost) 100 = differential input other settings : reserved r36 (24h) right mixer (1) 2:0 rmixsel 000 right input selection for output mix 000 = rinput1 001 = rinput2 011 = right adc input (after pga / micboost) 100 = differential input other settings : reserved table 21 output mixer signal selection register address bit label default description 8 ld2lo 0 left dac to left mixer 0 = disable (mute) 1 = enable path 7 li2lo 0 lmixsel signal to left mixer 0 = disable (mute) 1 = enable path r34 (22h) left mixer control (1) 6:4 li2lovol [2:0] 101 (-9db) lmixsel signal to left mixer volume 000 = +6db ? (3db steps) 111 = -15db 8 rd2lo 0 right dac to left mixer 0 = disable (mute) 1 = enable path 7 ri2lo 0 rmixsel signal to left mixer 0 = disable (mute) 1 = enable path r35 (23h) left mixer control (2) 6:4 ri2lovol [2:0] 101 (-9db) rmixsel signal to left mixer volume 000 = +6db ? (3db steps) 111 = -15db table 22 left output mixer control WM8987l production data w pd rev 4.0 august 2008 32 register address bit label default description 8 ld2ro 0 left dac to right mixer 0 = disable (mute) 1 = enable path 7 li2ro 0 lmixsel signal to right mixer 0 = disable (mute) 1 = enable path r36 (24h) right mixer control (1) 6:4 li2rovol [2:0] 101 (-9db) lmixsel signal to right mixer volume 000 = +6db ? (3db steps) 111 = -15db 8 rd2ro 0 right dac to right mixer 0 = disable (mute) 1 = enable path 7 ri2ro 0 rmixsel signal to right mixer 0 = disable (mute) 1 = enable path r37 (25h) right mixer control (2) 6:4 ri2rovol [2:0] 101 (-9db) rmixsel signal to right mixer volume 000 = +6db ? (3db steps) 111 = -15db table 23 right output mixer control the mono mixer differs from the left and right mixers in that the signal from each dac into the mono mixer is attenuated by 6db. this is to prevent overloading when left and right dac signals are mixed to mono. when driving a btl headset as shown in figure 46, monovol should be set 6db higher than the other output gains, in order to compensate for the 6db attenuation at the mono mixer. register address bit label default description 8 ld2mo 0 left dac to mono mixer 0 = disable (mute) 1 = enable path (-6db gain) 7 li2mo 0 lmixsel signal to mono mixer 0 = disable (mute) 1 = enable path r38 (26h) mono mixer control (1) 6:4 li2movol [2:0] 101 (-9db) lmixsel signal to mono mixer volume 000 = +6db ? (3db steps) 111 = -15db 8 rd2mo 0 right dac to mono mixer 0 = disable (mute) 1 = enable path 7 ri2mo 0 rmixsel signal to mono mixer 0 = disable (mute) 1 = enable path r39 (27h) mono mixer control (2) 6:4 ri2movol [2:0] 101 (-9db) rmixsel signal to mono mixer volume 000 = +6db ? (3db steps) 111 = -15db table 24 mono mixer control production data WM8987l w pd rev 4.0 august 2008 33 analogue outputs rout1 output rout1 is the non-inverting left-channel output for btl headsets (see page 54). it can drive 16 ? or 32 ? transducer loads. the rout1 signal volume can be adjusted under software control by writing to rout1vol. note that gains over 0db may cause clipping if the signal is large. any gain setting below 0101111 (minimum) mutes the output driver. the rout1 pin then remains at the same dc level (the reference voltage on the vref pin), so that no click noise is produced when muting or un- muting. a zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gain updates. a timeout is also available to update the gain in the case that zero cross detection is enabled but no zero crossing occurs. this function may be enabled by setting toen in register r23 (17h). register address bit label default description 8 ro1vu 0 rout1vol update for any change to rout1vol to take effect, write ?1? to this bit. 7 ro1zc 0 right zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r3 (03h) rout1 volume 6:0 rout1vol [6:0] 1111001 rout1 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute table 25 rout1 volume control lout2/rout2 outputs lout2 and rout2 are analogue output pins similar to rout1. for btl headsets, lout2 is the non-inverting left output and rout2 the inverting right output (with rout2inv=1); for single-ended headsets, lout2 is the left output and rout2 the right output. register address bit label default description 6:0 lout2vol [6:0] 1111001 (0db) lout2 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute 7 lo2zc 0 left zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r40 (28h) lout2 volume 8 lo2vu 0 lout2 volume update 0 = store lout2vol in intermediate latch (no gain change) 1 = update gain for both channels (left=lout2vol, right=from intermediate latch) WM8987l production data w pd rev 4.0 august 2008 34 register address bit label default description 6:0 rout2vol [6:0] 1111001 (0db) rout2 volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute 7 ro2zc 0 left zero cross enable 1 = change gain on zero cross only 0 = change gain immediately r41 (29h) rout2 volume 8 ro2vu 0 rout2 volume update 0 = store rout2vol in intermediate latch (no gain change) 1 = update gain for both channels (right=rout2vol, left=from intermediate latch) r24 (18h) additional control (2) 4 rout2inv 0 rout2 invert 0 = no inversion (0 phase shift) 1 = signal inverted (180 phase shift) table 26 lout2/rout2 volume control for single-ended operation, the lo2vu and ro2vu bits provide a method to ensure that the left and right channel gains are updated at the same time (irrespective of the time delay between writing to registers r40 and r41). out3 output the out3 pin can drive a 16 ? or 32 ? headphone or be used as a dc reference for a capless headphone output (see page 56). out3sw selects the mode of operation required. register address bit label default description r24 (18h) additional control (2) 8 out3sw 0 out3 select 0 : vref 1 : mono mixer (volume controlled by monovol) table 27 out3 select when out3sw=1, out3 drives out the inverted signal from the mono mixer. in this case, the mono mixer should be enabled (mono=1 in r26). the signal amplitude at the out3 output can be adjusted under software control by writing to monovol in r42. register address bit label default description 6:0 monovol [6:0] 1111001 (0db) mono mixer volume 1111111 = +6db ? (80 steps) 0110000 = -67db 0101111 to 0000000 = analogue mute r42 (2ah) mono mixer volume 7 mozc 0 mono mixer zero cross enable 1 = change gain on zero cross only 0 = change gain immediately table 28 mono mixer volume control production data WM8987l w pd rev 4.0 august 2008 35 enabling the outputs the analogue outputs and output mixers of the WM8987l can be separately enabled or disabled as shown in table 29. register address bit label default description 5 rout1 0 enables rout1 and right mixer 4 lout2 0 enables lout2 and left mixer 3 rout2 0 enables rout2 and right mixer 2 mono 0 enable mono mixer r26 (1ah) power management (2) 1 out3 0 enables out3 note: all ?enable? bits are 1 = on, 0 = off table 29 analogue output control all outputs and mixers are disabled by default. to save power, they should remain disabled whenever possible. outputs can be enabled at any time, except when vref is disabled (vr=0), as this may cause pop noise (see ?power management? and ?applications information? sections). whenever an analogue output is disabled, it remains connected to the vref voltage through an internal resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between vref and each output can be controlled using the vroi bit in register 27. the default is low (1.5k ? ), so that any capacitors on the outputs can charge up quickly at start-up. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 40k ? . register address bit label default description r27 (1bh) additional (1) 6 vroi 0 vref to analogue output resistance 0: 1.5 k ? 1: 40 k ? table 30 disabled outputs to vref resistance thermal shutdown the analogue outputs can drive large currents. to protect the WM8987l from overheating, a thermal shutdown circuit is included. if the device temperature reaches approximately 150 0 c and the thermal shutdown circuit is enabled (tsden = 1) then the output amplifiers (pins rout1, lout2, rout2 and out3) are disabled. register address bit label default description r23 (17h) additional control (1) 8 tsden 0 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled table 31 thermal shutdown WM8987l production data w pd rev 4.0 august 2008 36 digital audio interface the digital audio interface is used for inputting dac data into the WM8987l and outputting adc data from it. it uses five pins: ? adcdat: adc data output ? adclrc: adc data alignment clock ? dacdat: dac data input ? daclrc: dac data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, adclrc and daclrc can be outputs when the WM8987l operates as a master, or inputs when it is a slave (see master and slave mode operation, below). three different audio data formats are supported: ? i 2 s ? dsp mode ? left justified all of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the WM8987l can be configured as either a master or slave mode device. as a master device the WM8987l generates bclk, adclrc and daclrc and thus controls sequencing of the data transfer on adcdat and dacdat. in slave mode, the WM8987l responds with data to clocks it receives over the digital audio interface. the mode can be selected by writing to the ms bit (see table 23). master and slave modes are illustrated below. figure 11 master mode figure 12 slave mode note: for optimum adc audio performance in slave mode, the bclk input signal should be configured to transition at the same time as the falling edge of mclk. the adcdat digital data output is buffered inside the codec using a digital logic buffering block. however, the adcdat buffering block is not reset by the power-on reset circuit and hence the adcdat pin stage (logic high or logic low) is undefined at power up until data is clocked out from the adc. implementation of either of these workarounds will ensure correct operation: ? ensure that any external connection to the adcdat pin is made with the understanding that adcdat pin may be driven high or low by the codec until adc data is clocked out. ? tri-state the adcdat output pin by setting the tri bit in r24 (additional control 2 register). setting this bit will also configure adclrc, daclrc and bclk as inputs and (as the codec has no internal pull-up/down resistors) the input voltage level must be set on these pins by an external source (either the device connected to the digital audio interface or pull-up/down resistors) to prevent excess current consumption. production data WM8987l w pd rev 4.0 august 2008 37 audio data formats in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 13 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 14 i 2 s justified audio interface (assuming n-bit word length) in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 15 and figure 16. in device slave mode, figure 17 and figure 18, it is possible to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. WM8987l production data w pd rev 4.0 august 2008 38 figure 15 dsp/pcm mode audio interface (mode a, lrp=0, master) figure 16 dsp/pcm mode audio interface (mode b, lrp=1, master) figure 17 dsp/pcm mode audio interface (mode a, lrp=0, slave) figure 18 dsp/pcm mode audio interface (mode b, lrp=0, slave) production data WM8987l w pd rev 4.0 august 2008 39 audio interface control the register bits controlling audio format, word length and master / slave mode are summarised in table 32. ms selects audio interface operation in master or slave mode. in master mode bclk, adclrc and daclrc are outputs. the frequency of adclrc and daclrc is set by the sample rate control bits sr[4:0] and usb. in slave mode bclk, adclrc and daclrc are inputs. register address bit label default description 6 ms 0 master / slave mode control 1 = enable master mode 0 = enable slave mode 5 lrswap 0 left/right channel swap 1 = swap left and right dac data in audio interface 0 = output left and right data as normal right, left and i2s modes ? lrclk polarity 1 = invert lrclk polarity 0 = normal lrclk polarity 4 lrp 0 dsp mode ? mode a/b select 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 3:2 wl[1:0] 10 audio data word length 11 = 32 bits (see note) 10 = 24 bits 01 = 20 bits 00 = 16 bits r7 (07h) digital audio interface format 1:0 format[1:0] 10 audio data format select 11 = dsp mode 10 = i 2 s format 01 = left justified 00 = reserved table 32 audio data format control audio interface output tristate register bit tri, register 24(18h) bit[3] can be used to tristate the adcdat pin and switch adclrc, daclrc and bclk to inputs. in slave mode (master=0) adclrc, daclrc and bclk are by default configured as inputs and only adcdat will be tri-stated, (see table 33). register address bit label default description r24(18h) additional control (2) 3 tri 0 tristates adcdat and switches adclrc, daclrc and bclk to inputs. 0 = adcdat is an output, adclrc, daclrc and bclk are inputs (slave mode) or outputs (master mode) 1 = adcdat is tristated, adclrc, daclrc and bclk are inputs table 33 tri-stating the audio interface WM8987l production data w pd rev 4.0 august 2008 40 master mode adclrc and daclrc enable in master mode, by default adclrc is disabled when the adc is disabled and daclrc is disabled when the dac is disabled. register bit lrcm, register 24(18h) bit[2] changes the control so that the adclrc and daclrc are disabled only when adc and dac are disabled. this enables the user to use e.g. adclrc for both adc and dac lrclk and disable the adc when dac only operation is required, (see table 34). register address bit label default description r24(18h) additional control (2) 2 lrcm 0 selects disable mode for adclrc and daclrc 0 = adclrc disabled when adc (left and right) disabled, daclrc disabled when dac (left and right) disabled. 1 = adclrc and daclrc disabled only when adc (left and right) and dac (left and right) are disabled. table 34 adclrc/daclrc enable bit clock mode the default master mode bit clock generator produces a bit clock frequency based on the sample rate and input mclk frequency as shown in table 38. when enabled by setting the appropriate bcm[1:0] bits, the bit clock mode (bcm) function overrides the default master mode bit clock generator to produce the bit clock frequency shown in the table below: register address bit label default description r8 (08h) clocking and sample rate control 8:7 bcm[1:0] 00 bclk frequency 00 = bcm function disabled 01 = mclk/4 10 = mclk/8 11 = mclk/16 table 35 master mode bclk frequency control the bcm mode bit clock generator produces 16 or 24 bit clock cycles per sample. the number of bit clock cycles per sample in this mode is determined by the word length bits (wl[1:0]) in the digital audio interface format register (r7). when these bits are set to 00, there will be 16 bit clock cycles per sample. when these bits are set to 01, 10 or 11, there will be 24 bit clock cycles per sample. please refer to figure 19. the bcm generator uses the adclrc signal, hence the adclrc signal must be enabled when using bit clock mode. to enable the adclrc signal, either the adc must be powered up or, if the adc is not in use, the lrcm bit must be set to enable both the adclrc and daclrc signals when either the adc or the dac is enabled. when the bcm function is enabled, the following restrictions apply: 1. the dac and adc must be operated at the same sample rate. 2. dsp late digital audio interface mode is not available and must not be enabled. figure 19 bit clock mode production data WM8987l w pd rev 4.0 august 2008 41 note: the shaded bit clock cycles are present only when 24-bit mode is selected. please refer to the "bit clock mode" description for details. if bclk frequency is high enough for the increased tdda propagation delay (i.e. adcdat propagation delay from bclk falling edge) to cause an adcdat set-up time issue (i.e. the adcdat signal is delayed such that the first bit of adcdat data appears during the second bclk cycle), the bcm[1:0] bclk divider bits should be configured to reduce the bclk frequency. clock output by default, the adclrc pin is the adc word clock input/output. under the control of adclrm[1:0], register 27(1bh) bits [8:7] the adclrc pin may be configured as a clock output. if adclrm is 01, 10 or 11 then adclrc pin is always an output even in slave mode or when tri = ?1?, (see table 36). the adc then uses the daclrc pin as its lrclk in both master and slave modes. register address bit label default description r27(1bh) additional control (3) [8:7] adclrm [1:0] 00 configures adclrc pin 00 = adclrc is adc word clock input (slave mode) or adclrc output (master mode) 01 = adclrc pin is mclk output 10 = adclrc pin is mclk / 5.5 output 11 = adclrc pin is mclk / 6 output table 36 adclrc clock output clocking and sample rates the WM8987l supports a wide range of master clock frequencies on the mclk pin, and can generate many commonly used audio sample rates directly from the master clock. the adc and dac do not need to run at the same sample rate; several different combinations are possible. there are two clocking modes: ? ?normal? mode supports master clocks of 128f s , 192f s , 256f s , 384f s , and their multiples ( note: f s refers to the adc or dac sample rate, whichever is faster) ? usb mode supports 12mhz or 24mhz master clocks. this mode is intended for use in systems with a usb interface, and eliminates the need for an external pll to generate another clock frequency for the audio codec. register address bit label default description 6 clkdiv2 0 master clock divide by 2 1 = mclk is divided by 2 0 = mclk is not divided 5:1 sr [4:0] 00000 sample rate control r8 (08h) clocking and sample rate control 0 usb 0 clocking mode select 1 = usb mode 0 = ?normal? mode table 37 clocking and sample rate control the clocking of the WM8987l is controlled using the clkdiv2, usb, and sr control bits. setting the clkdiv2 bit divides mclk by two internally. the usb bit selects between ?normal? and usb mode. each value of sr[4:0] selects one combination of mclk division ratios and hence one combination of sample rates (see next page). since all sample rates are generated by dividing mclk, their accuracy depends on the accuracy of mclk. if mclk changes, the sample rates change proportionately. note that some sample rates (e.g. 44.1khz in usb mode) are approximated, i.e. they differ from their target value by a very small amount. this is not audible, as the maximum deviation is only 0.27% (8.0214khz instead of 8khz in usb mode). by comparison, a half-tone step corresponds to a 5.9% change in pitch. the sr[4:0] bits must be set to configure the appropriate adc and dac sample rates in both master and slave mode. note: when the adc is configured at a sample rate of 88.2, 88.235 or 96khz (sr[4:0]), the adc right channel data output will be delayed by one sample relative to the left channel data. WM8987l production data w pd rev 4.0 august 2008 42 mclk clkdiv2=0 mclk clkdiv2=1 adc sample rate (adclrc) dac sample rate (daclrc) usb sr [4:0] filter type bclk (ms=1) ?normal? clock mode (?*? indicates backward compatibility with wm8731) 8 khz (mclk/1536) 8 khz (mclk/1536) 0 00110 * 1 mclk/4 8 khz (mclk/1536) 48 khz (mclk/256) 0 00100 * 1 mclk/4 12 khz (mclk/1024) 12 khz (mclk/1024) 0 01000 1 mclk/4 16 khz (mclk/768) 16 khz (mclk/768) 0 01010 1 mclk/4 24 khz (mclk/512) 24 khz (mclk/512) 0 11100 1 mclk/4 32 khz (mclk/384) 32 khz (mclk/384) 0 01100 * 1 mclk/4 48 khz (mclk/256) 8 khz (mclk/1536) 0 00010 * 1 mclk/4 48 khz (mclk/256) 48 khz (mclk/256) 0 00000 * 1 mclk/4 12.288 mhz 24.576 mhz 96 khz (mclk/128) 96 khz (mclk/128) 0 01110 * 3 mclk/2 8.0182 khz (mclk/1408) 8.0182 khz (mclk/1408) 0 10110 * 1 mclk/4 8.0182 khz (mclk/1408) 44.1 khz (mclk/256) 0 10100 * 1 mclk/4 11.025 khz (mclk/1024) 11.025 khz (mclk/1024) 0 11000 1 mclk/4 22.05 khz (mclk/512) 22.05 khz (mclk/512) 0 11010 1 mclk/4 44.1 khz (mclk/256) 8.0182 khz (mclk/1408) 0 10010 * 1 mclk/4 44.1 khz (mclk/256) 44.1 khz (mclk/256) 0 10000 * 1 mclk/4 11.2896mhz 22.5792mhz 88.2 khz (mclk/128) 88.2 khz (mclk/128) 0 11110 * 3 mclk/2 8 khz (mclk/2304) 8 khz (mclk/2304) 0 00111 * 1 mclk/6 8 khz (mclk/2304) 48 khz (mclk/384) 0 00101 * 1 mclk/6 12 khz (mclk/1536) 12 khz (mclk/1536) 0 01001 1 mclk/6 16khz (mclk/1152) 16 khz (mclk/1152) 0 01011 1 mclk/6 24khz (mclk/768) 24 khz (mclk/768) 0 11101 1 mclk/6 32 khz (mclk/576) 32 khz (mclk/576) 0 01101 * 1 mclk/6 48 khz (mclk/384) 48 khz (mclk/384) 0 00001 * 1 mclk/6 48 khz (mclk/384) 8 khz (mclk/2304) 0 00011 * 1 mclk/6 18.432mhz 36.864mhz 96 khz (mclk/192) 96 khz (mclk/192) 0 01111 * 3 mclk/3 8.0182 khz (mclk/2112) 8.0182 khz (mclk/2112) 0 10111 * 1 mclk/6 8.0182 khz (mclk/2112) 44.1 khz (mclk/384) 0 10101 * 1 mclk/6 11.025 khz (mclk/1536) 11.025 khz (mclk/1536) 0 11001 1 mclk/6 22.05 khz (mclk/768) 22.05 khz (mclk/768) 0 11011 1 mclk/6 44.1 khz (mclk/384) 8.0182 khz (mclk/2112) 0 10011 * 1 mclk/6 44.1 khz (mclk/384) 44.1 khz (mclk/384) 0 10001 * 1 mclk/6 16.9344mhz 33.8688mhz 88.2 khz (mclk/192) 88.2 khz (mclk/192) 0 11111 * 3 mclk/3 usb mode (?*? indicates backward compatibility with wm8731) 8 khz (mclk/1500) 8 khz (mclk/1500) 1 00110 * 0 mclk 8 khz (mclk/1500) 48 khz (mclk/250) 1 00100 * 0 mclk 8.0214 khz (mclk/1496) 8.0214khz (mclk/1496) 1 10111 * 1 mclk 8.0214 khz (mclk/1496) 44.118 khz (mclk/272) 1 10101 * 1 mclk 11.0259 khz (mclk/1088) 11.0259khz (mclk/1088) 1 11001 1 mclk 12 khz (mclk/1000) 12 khz (mclk/1000) 1 01000 0 mclk 16khz (mclk/750) 16khz (mclk/750) 1 01010 0 mclk 22.0588khz (mclk/544) 22.0588khz (mclk/544) 1 11011 1 mclk 24khz (mclk/500) 24khz (mclk/500) 1 11100 0 mclk 32 khz (mclk/375) 32 khz (mclk/375) 1 01100 * 0 mclk 44.118 khz (mclk/272) 8.0214khz (mclk/1496) 1 10011 * 1 mclk 44.118 khz (mclk/272) 44.118 khz (mclk/272) 1 10001 * 1 mclk 48 khz (mclk/250) 8 khz (mclk/1500) 1 00010 * 0 mclk 48 khz (mclk/250) 48 khz (mclk/250) 1 00000 * 0 mclk 88.235khz (mclk/136) 88.235khz (mclk/136) 1 11111 * 3 mclk 12.000mhz 24.000mhz 96 khz (mclk/125) 96 khz (mclk/125) 1 01110 * 2 mclk table 38 master clock and sample rates production data WM8987l w pd rev 4.0 august 2008 43 control interface selection of control mode the WM8987l is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are data bits, corresponding to the 9 bits in each control register. the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin selects the interface format. mode interface format low 2 wire high 3 wire table 39 control interface mode selection 3-wire serial control mode in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb latches in a complete control word consisting of the last 16 bits. b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sdin sclk csb control register address control register data bits latch figure 20 3-wire serial control interface 2-wire serial control mode the WM8987l supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8987l). the WM8987l operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the WM8987l and the r/w bit is ?0?, indicating a write, then the WM8987l responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1?, the WM8987l returns to the idle condition and wait for a new start condition and valid address. once the WM8987l has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the WM8987l register address plus the first bit of register data). the WM8987l then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the WM8987l acknowledges again by pulling sdin low. the transfer of data is complete when there is a low to high transition on sdin while sclk is high. after receiving a complete address and data sequence the WM8987l returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 2 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 21 2-wire serial control interface WM8987l production data w pd rev 4.0 august 2008 44 the WM8987l has two possible device addresses, which can be selected using the csb pin. csb state device address low 0011010 (0 x 34h) high 0011011 (0 x 36h) table 40 2-wire mpu interface address selection power supplies the WM8987l can use up to four separate power supplies: ? avdd / agnd: analogue supply, powers all analogue functions except the headphone drivers. avdd can range from 1.8v to 3.6v and has the most significant impact on overall power consumption (except for power consumed in the headphone). a large avdd slightly improves audio quality. ? hpvdd / hpgnd: headphone supply, powers the headphone drivers. hpvdd is normally tied to avdd, but it requires separate layout and decoupling capacitors to curb harmonic distortion. if hpvdd is lower than avdd, the output signal may be clipped. ? dcvdd: digital core supply, powers all digital functions except the audio and control interfaces. dcvdd can range from 1.42v to 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. ? dbvdd: digital buffer supply, powers the audio and control interface buffers. this makes it possible to run the digital core at very low voltages, saving power, while interfacing to other digital devices using a higher voltage. dbvdd draws much less power than dcvdd, and has no effect on audio quality. dbvdd can range from 1.8v to 3.6v. the return path for dbvdd is dgnd, which is shared with dcvdd. it is possible to use the same supply voltage on all four. however, digital and analogue supplies should be routed and decoupled separately to keep digital switching noise out of the analogue signal paths. production data WM8987l w pd rev 4.0 august 2008 45 power management the WM8987l has two control registers that allow users to select which functions are active. for minimum power consumption, unused functions should be disabled. to avoid any pop or click noise, it is important to enable or disable functions in the correct order (see applications information). vmidsel is the enable for the vmid reference, which defaults to disabled and can be enabled as a 50k ? potential divider or, for low power maintenance of vref when all other blo cks are disabled, as a 500k ? potential divider. register address bit label default description 8:7 vmidsel 00 vmid divider enable and select 00 ? vmid disabled (for off mode) 01 ? 50k ? divider enabled (for playback/record) 10 ? 500k ? divider enabled (for low-power standby) 11 ? 5k ? divider enabled (for fast start-up) 6 vref 0 vref (necessary for all other functions) 5 ainl 0 analogue in pga left 4 ainr 0 analogue in pga right 3 adcl 0 adc left 2 adcr 0 adc right r25 (19h) power management (1) 1 micb 0 micbias 8 dacl 0 dac left 7 dacr 0 dac right 5 rout1 0 rout1 output buffer 4 lout2 0 lout2 output buffer 3 rout2 0 rout2 output buffer 2 mono 0 mono mixer r26 (1ah) power management (2) 1 out3 0 out3 output buffer notes: 1. all bits except vmidsel are 1=on, 0=off. 2. the left mixer is enabled when lout2=1. 3. the right mixer is enabled when rout1=1 or rout2=1. 4. the mono mixer is enabled when mono=1. table 41 power management stopping the master clock in order to minimise power consumed in the digital core of the WM8987l, the master clock may be stopped in standby and off modes. if this cannot be done externally at the clock source, the digenb bit (r25, bit 0) can be set to stop the mclk signal from propagating into the device core. in standby mode, setting digenb will typically provide an additional power saving on dcvdd of 20ua. however, since setting digenb has no effect on the power consumption of other system components external to the WM8987l, it is preferable to disable the master clock at its source wherever possible. register address bit label default description r25 (19h) additional control (1) 0 digenb 0 master clock disable 0: master clock enabled 1: master clock disabled table 42 adc and dac oversampling rate selection note: before digenb can be set, the control bits adcl, adcr, dacl and dacr must be set to zero and a waiting time of 1ms must be observed. any failure to follow this procedure may prevent dacs and adcs from re-starting correctly. WM8987l production data w pd rev 4.0 august 2008 46 saving power by reducing oversampling rate the default mode of operation of the adc and dac digital filters is in 128x oversampling mode. under the control of adcosr and dacosr the oversampling rate may be halved. this will result in a slight decrease in noise performance but will also reduce the power consumption of the device. in usb mode adcosr must be set to 0, i.e. 128x oversampling. register address bit label default description 1 adcosr 0 adc oversample rate select 1 = 64x (lowest power) 0 = 128x (best snr) r24 (18h) additional control (2) 0 dacosr 0 dac oversample rate select 1 = 64x (lowest power) 0 = 128x (best snr) table 43 adc and dac oversampling rate selection adcosr set to ?1?, 64x oversample mode, is not supported in usb mode (usb=1). saving power at higher supply voltages the analogue supplies to the WM8987l can run from 1.8v to 3.6v. by default, all analogue circuitry on the device is optimized to run at 3.3v. this set-up is also good for all other supply voltages down to 1.8v. at lower voltages, performance can be improved by increasing the bias current. if low power operation is preferred the bias current can be left at the default setting. this is controlled as shown below. register address bit label default description r23 (17h) additional control(1) 7:6 vsel [1:0] 11 analogue bias optimization 00: highest bias current, optimized for avdd=1.8v 01: bias current optimized for avdd=2.5v 1x: lowest bias current, optimized for avdd=3.3v production data WM8987l w pd rev 4.0 august 2008 47 register map register address (bit 15 ? 9) remarks bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] default page ref r0 (00h) 0000000 left input volume livu linmute lizc linvol 010010111 20 r1 (01h) 0000001 right input volume rivu rinmute rizc rinvol 010010111 20 r2 (02h) 0000010 reserved n/a n/a n/a r3 (03h) 0000011 rout1 volume ro1vu ro1zc rout1vol[6:0] 001111001 33 r4 (04h) 0000100 reserved n/a n/a n/a r5 (05h) 0000101 adc & dac control adcdiv2 dacdiv2 adcpol[1:0] hpor dacmu deemph[1:0] adchpd 000001000 22, 27, 30 r6 (06h) 0000110 reserved 0 0 0 0 0 0 0 0 0 000000000 n/a r7 (07h) 0000111 audio interface 0 0 ms lrswap lrp wl[1:0] format[1:0] 000001010 39 r8 (08h) 0001000 sample rate bcm[1:0] clkdiv2 sr[4:0] usb 000000000 40, 41 r9 (09h) 0001001 reserved 0 0 0 0 0 0 0 0 0 000000000 n/a r10 (0ah) 0001010 left dac volume ldvu ldacvol[7:0] 011111111 28 r11 (0bh) 0001011 right dac volume rdvu rdacvol[7:0] 011111111 28 r12 (0ch) 0001100 bass contro l 0 bb bc 0 0 bass[3:0] 000001111 29 r13 (0dh) 0001101 treble control 0 0 tc 0 0 trbl[3:0] 000001111 29 r15 (0fh) 0001111 reset writing to this register resets all registers to their default state not reset n/a r16 (10h) 0010000 3d control 0 mode3d 3duc 3dlc 3ddepth[3:0] 3den 000000000 27 r17 (11h) 0010001 alc1 alcsel[1:0] maxgain[2:0] alcl[3:0] 001111011 25 r18 (12h) 0010010 alc2 0 alczc 0 0 0 hld[3:0] 000000000 25 r19 (13h) 0010011 alc3 0 dcy[3:0] atk[3:0] 000110010 25 r20 (14h) 0010100 noise gate 0 ngth[4:0] ngg[1:0] ngat 000000000 26 r21 (15h) 0010101 left adc volume lavu ladcvol[7:0] 011000011 23 r22 (16h) 0010110 right adc volume ravu radcvol[7:0] 011000011 23 r23 (17h) 0010111 additional contro l(1) tsden vsel[1:0] dmonomix[1:0] datsel[1:0] dacinv toen 011000000 19, 20, 30, 35, 46 r24 (18h) 0011000 additional control(2) out3sw 0 0 0 rout2inv tri lrcm adcosr dacosr 000000000 34, 39, 40, 46 r25 (19h) 0011001 pwr mgmt (1) vmidsel[1:0] vref ainl ainr adcl adcr micb digenb 000000000 45 r26 (1ah) 0011010 pwr mgmt (2) dacl dacr 0 rout1 lout2 rout2 mono out3 0 000000000 35, 45 r27 (1bh) 0011011 additional control (3) adclrm[1:0] vroi hpflren 0 0 0 0 0 000000000 22, 35, 41 r31 (1fh) 0011111 adc input mode ds monomix[1:0] rdcm ldcm 0 0 0 0 000000000 17, 18 r32 (20h) 0100000 adcl signal path 0 linsel[1:0] lmicboost[1:0] 0 0 0 0 000000000 18 r33 (21h) 0100001 adcr signal path 0 rinsel[1:0] rmicboost[1:0] 0 0 0 0 000000000 18 r34 (22h) 0100010 left out mix (1) ld2lo li2lo li2lovol[2:0] 0 lmixsel[2:0] 001010000 31 r35 (23h) 0100011 left out mix (2) rd2lo ri2lo ri2lovol[2:0] 0 0 0 0 001010000 31 r36 (24h) 0100100 right out mix (1) ld2ro li2ro li2rovol[2:0] 0 rmixsel[2 :0] 001010000 31, 32 r37 (25h) 0100101 right out mix (2) rd2ro ri2ro ri2rovol[2:0] 0 0 0 0 001010000 32 r38 (26h) 0100110 mono mix (1) ld2mo li2mo li2movol[2:0] 0 0 0 0 001010000 32 r39 (27h) 0100111 mono mix (2) rd2mo ri2mo ri2movol[2:0] 0 0 0 0 001010000 32 r40 (28h) 0101000 lout2 volume lo2vu lo2zc lout2vol[6:0] 001111001 33 r41 (29h) 0101001 rout2 volume ro2vu ro2zc rout2vol[6:0] 001111001 34 r42 (2ah) 0101010 mono mixer volume 0 mozc monovol[6:0] 001111001 34 WM8987l production data w pd rev 4.0 august 2008 48 digital filter characteristics the adc and dac employ different digital filters. there are 4 types of digital filter, called type 0, 1, 2 and 3. the performance of types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. parameter test conditions min typ max unit adc filter type 0 (usb mode, 250fs operation) +/- 0.05db 0 0.416fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.584fs stopband attenuation f > 0.584fs -60 db adc filter type 1 (usb mode, 272fs or normal mode operation) +/- 0.05db 0 0.4535fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.5465fs stopband attenuation f > 0.5465fs -60 db -3db 3.7 -0.5db 10.4 high pass filter corner frequency -0.1db 21.6 hz dac filter type 0 (usb mode, 250fs operation) +/- 0.03db 0 0.416fs passband -6db 0.5fs passband ripple +/-0.03 db stopband 0.584fs stopband attenuation f > 0.584fs -50 db dac filter type 1 (usb mode, 272fs or normal mode operation) +/- 0.03db 0 0.4535fs passband -6db 0.5fs passband ripple +/- 0.03 db stopband 0.5465fs stopband attenuation f > 0.5465fs -50 db table 44 digital filter characteristics dac filters adc filters mode group delay mode group delay 0 (250 usb) 11/fs 0 (250 usb) 13/fs 1 (256/272) 16/fs 1 (256/272) 23/fs 2 (250 usb, 96k mode) 4/fs 2 (250 usb, 96k mode) 4/fs 3 (256/272, 88.2/96k mode) 3/fs 3 (256/272, 88.2/96k mode) 5/fs table 45 adc/dac digital filters group delay terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region production data WM8987l w pd rev 4.0 august 2008 49 dac filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 22 dac digital filter frequency response ? type 0 figure 23 dac digital filter ripple ? type 0 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 24 dac digital filter frequency response ? type 1 figure 25 dac digital filter ripple ? type 1 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 26 dac digital filter frequency response ? type 2 figure 27 dac digital filter ripple ? type 2 WM8987l production data w pd rev 4.0 august 2008 50 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 28 dac digital filter frequency response ? type 3 figure 29 dac digital filter ripple ? type 3 adc filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 30 adc digital filter frequency response ? type 0 figure 31 adc digital filter ripple ? type 0 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 32 adc digital filter frequency response ? type 1 figure 33 adc digital filter ripple ? type 1 production data WM8987l w pd rev 4.0 august 2008 51 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 34 adc digital filter frequency response ? type 2 figure 35 adc digital filter ripple ? type 2 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 36 adc digital filter frequency response ? type 2 figure 37 adc digital filter ripple ? type 3 de-emphasis filter responses -10 -8 -6 -4 -2 0 0 2000 4000 6000 8000 10000 12000 14000 16000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 2000 4000 6000 8000 10000 12000 14000 16000 response (db) frequency (fs) figure 38 de-emphasis frequency response (32khz) figure 39 de-emphasis error (32khz) WM8987l production data w pd rev 4.0 august 2008 52 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5000 10000 15000 20000 response (db) frequency (fs) figure 40 de-emphasis frequency response (44.1khz) figure 41 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 response (db) frequency (fs) -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 5000 10000 15000 20000 response (db) frequency (fs) figure 42 de-emphasis frequency response (48khz) figure 43 de-emphasis error (48khz) highpass filter the WM8987l has a selectable digital highpass filter in the adc filter path to remove dc offsets. the filter response is characterised by the following polynomial: figure 44 adc highpass filter response 1 - z -1 1 - 0.9995z -1 h(z) = -15 -10 -5 0 0 0.0005 0.001 0.0015 0.002 response (db) frequency (fs) production data WM8987l w pd rev 4.0 august 2008 53 applications information recommended external components figure 45 recommended external components diagram WM8987l production data w pd rev 4.0 august 2008 54 driving btl headsets to drive bridge-tied load (btl) headsets, the analogue outputs should be used as follows: ? rout1 is the non-inverting right output (hpr+) ? lout2 is the non-inverting left output (hpl+) ? rout2 is the inverting right output (hpr-) ? out3 is the inverting left output (hpl-) this setup is illustrated in figure 46. figure 46 driving a btl headset it requires the following register settings: ? set the rout1, lout2, rout2, mono and out3 bits in r26 to ?1? to enable the outputs and associated mixers. ? set ld2lo (r34), rd2ro (r37), ld2mo (r38) and out3sw (r24) to ?1? to enable the correct audio paths (in the case of audio playback from an analogue source, select the input pin using lmixsel and rmixsel, and set li2lo/li2mo/ri2ro instead of ld2lo/ld2mo/rd2ro). ? set rout2inv = 1 in r24 to invert the right-channel signal going to rout2. ? the left channel volume is controlled by lout2vol and monovol. to get the same rms signal level at both pins, monovol should be set 6db higher than lout2vol. ? the right channel volume is controlled by rout1vol and rout2vol. both should be set to the same value. to get the same gain as in the left channel, this value should be the same as lout2vol. note that this method for driving headsets can only be used where both ends of each transducer are electrically separate. it is incompatible with standard 2.5mm or 3.5mm headphone jacks, where a common ground serves as the return path for both left and right transducers. driving single-ended headphones using capacitors to drive single-ended headphones using dc blocking capacitors, the analogue outputs should be used as follows: ? lout2 is the left output ? rout2 is the right output ? rout1 and out3 are unused and should be disabled this setup is illustrated in figure 47. production data WM8987l w pd rev 4.0 august 2008 55 figure 47 driving single-ended headphones using dc-blocking capacitors it requires the following register settings: ? set only the lout2 and rout2 bits in r26 to ?1? to enable lout2, rout2 and the associated mixers. the rout1, mono and out3 bits should remain at ?0?. ? set ld2lo (r34) and rd2ro (r37) to ?1? to enable the correct audio paths (in the case of audio playback from an analogue source, select the input pin using lmixsel and rmixsel, and set li2lo/ri2ro instead of ld2lo/rd2ro). ? leave rout2inv = 0 in r24, so that the right-channel signal going to rout2 is not inverted. ? the left channel volume is controlled by lout2vol. ? the right channel volume is controlled by rout2vol. this method for driving a headphone requires two capacitors in the lout2 and rout2 paths. their capacitance c and the load resistance r together determine the lower cut-off frequency, f c . increasing r or c lowers f c , improving the bass response. smaller capacitance values will diminish the bass response. for example, assuming a 16 ohm load and c = 220 f: f c = 1 / 2 r l c 1 = 1 / (2 x 16 ? x 220 f) = 45 hz capless drive to drive single-ended headphones without dc blocking capacitors, the analogue outputs should be used as follows: ? lout2 is the left output ? rout2 is the right output ? out3 is a pseudo-ground output for the headphone ? rout1 is unused and should be disabled this setup is illustrated in figure 47. WM8987l production data w pd rev 4.0 august 2008 56 figure 48 driving single-ended headphones without dc-blocking capacitors it requires the following register settings: ? set only the lout2, rout2 and out3 bits in r26 to ?1? to enable lout2, rout2, out3 and the associated mixers. the rout1 and mono bits should remain at ?0?. ? set ld2lo (r34) and rd2ro (r37) to ?1? to enable the correct audio paths (in the case of audio playback from an analogue source, select the input pin using lmixsel and rmixsel, and set li2lo/ri2ro instead of ld2lo/rd2ro). ? leave out3sw = 0 in r24, so that the potential at out3 is the same as vref. ? leave rout2inv = 0 in r24, so that the right-channel signal going to rout2 is not inverted. ? the left channel volume is controlled by lout2vol. ? the right channel volume is controlled by rout2vol. as the out3 pin produces a dc voltage of avdd/2 (=vref), there is no dc offset between lout2/rout2 and out3, and therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. however, compared to the single-ended configuration using capacitors, the WM8987l power consumption is higher, due to the additional power consumed in the out3 driver. it is recommended to connect the capless headphone outputs only to headphones, and not to the line input of another system. although the built-in thermal shutdown circuit will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other system is grounded. microphone input configuration figure 49 recommended circuit for line input r2 47kohm c1 220pf c2 1uf agnd agnd agnd linput1/2 rinput1/2 from microphone r1 680 ohm to 2.2kohm check microphone's specification micbias production data WM8987l w pd rev 4.0 august 2008 57 for interfacing to a microphone, the alc function should be enabled and the microphone boost switched on. microphones held close to a speaker?s mouth would normally use the 13db gain setting, while tabletop or room microphones would need a 29db boost. the recommended application circuit is shown above. r1 and r2 form part of the biasing network (refer to microphone bias section). r1 connected to micbias is necessary only for electret type microphones that require a voltage bias. r2 should always be present to prevent the microphone input from charging to a high voltage which may damage the microphone on connection. r1 and r2 should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2kohm. c1 together with the source impedance of the microphone and the WM8987l input impedance forms an rf filter. c2 is a dc blocking capacitor to allow the microphone to be biased at a different dc voltage to the micin signal. line input configuration when linput1/rinput1 or linput2/rinput2 are used as line inputs, the microphone boost and alc functions should normally be disabled. in order to avoid clipping, the user must ensure that the input signal does not exceed avdd. this may require a potential divider circuit in some applications. it is also recommended to remove rf interference picked up on any cables using a simple first-order rc filter, as high-frequency components in the input signal may otherwise cause aliasing distortion in the audio band. ac signals with no dc bias should be fed to the WM8987l through a dc blocking capacitor, e.g. 1 f. minimising pop noise at the analogue outputs to minimise any pop or click noise when the system is powered up or down, the following procedures are recommended. power up ? switch on power supplies. by default the WM8987l is in standby mode, the dac is digitally muted and the audio interface and analogue outputs are all off (dacmu = 1 power management registers 1 and 2 are all zeros). ? enable vmid and vref. ? enable dacs as required ? enable line and / or headphone output buffers as required. ? set dacmu = 0 to soft-un-mute the audio dacs. power down ? set dacmu = 1 to soft-mute the audio dacs. ? disable all output buffers. ? switch off the power supplies. power management examples power management (1) power management (2) pgas adcs dacs output buffers operation mode vmidsel vref ainl ainr adcl adcr micb 0 digenb 1 dacl dacr rout1 lout2 rout2 mono out3 low-power standby 10 1 0 0 0 0 0 0 0 0 0 0 0 0 0 btl headset stereo playback 01 1 0 0 0 0 0 1 1 1 1 1 1 1 1 btl headset phone call 01 1 1 0 1 0 1 1 1 0 1 1 1 1 1 single-ended headset stereo playback 01 1 0 0 0 0 0 1 1 1 0 1 1 0 0 single-ended headset phone call 01 1 1 0 1 0 1 1 1 0 0 1 1 0 0 single-ended headset stereo playback (capless) 01 1 0 0 0 0 0 1 1 1 0 1 1 0 1 single-ended headset phone call (capless) 01 1 1 0 1 0 1 1 1 0 0 1 1 0 1 table 46 example register settings for power management WM8987l production data w pd rev 4.0 august 2008 58 package dimensions dm043.f fl: 28 pin col qfn plastic package 4 x 4 x 0.75 mm body, 0.45 mm lead pitch index area (d/2 x e/2) top view d e 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vggd-2. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to applications note wan_0118 for further information regarding pcb footprints and qfn package soldering. 7. depending on the method of lead termination at the edge of the package, pull back (l1) may be present. 8. this drawing is subject to change without notice. detail 1 a 7 1 15 21 28 22 14 e 8 1 b c bbb m a bottom view c aaa 2 x c aaa 2 x c a3 seating plane detail 2 a1 c 0.08 c ccc a 5 side view l detail 1 e datum detail 2 terminal tip e/2 1 r see detail 2 b a3 g t h w exposed lead detail 2 l1 dimensions (mm) symbols min nom max note a a1 a3 0.725 0.75 0.775 0.05 0.02 0 0.203 ref b d e e l 0.28 0.18 4.00 0.45 bsc 0.40 ref 4.00 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220 tolerances of form and position 0.23 h 0.100 ref 0.535 ref g t 0.100 ref w 0.230 ref 1 l1 0.05 ref 7 3.95 4.05 3.95 4.05 pin 1 identification 0.150mm square 0.275mm 0.275mm b production data WM8987l w pd rev 4.0 august 2008 59 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com |
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